1. Field of the Invention
The present invention relates to a semiconductor memory circuit and, more specifically, to a semiconductor memory circuit having a function of latching data until its subsequent data is determined in a sense amplifier in order to stably read out the data.
2. Description of the Related Art
FIGS. 1A and 1B are circuit diagrams showing a readout system of a conventional nonvolatile memory. In the circuit of FIG. 1A, a bit line (column selection line) is selected as follows. Address signals are supplied from an address pin to a column decoder 21 of first stage and a column decoder 22 of second stage through an address buffer 1. In each of the column decoders 21 and 22, a NAND gate 23 and an inverter 24 are connected in series, as shown in FIG. 1B, and then connected to the gates of selecting transistors 11. The first-stage column decoder 21 outputs a first selection signal SS1 and the second-stage column decoder 22 outputs a second selection signal SS2 to turn on the selecting transistors 11(a) and 11(b), respectively. Thus, one bit line BT is selected from a memory cell array 3. In contrast, an address signal is supplied to a row selection circuit 4 through the address buffer 1, and one word line (row selection line) WL is selected from the memory cell array 3. Data of a memory cell at the crossing point of the selected bit and word lines is transmitted to a sense amplifier 5 via the selecting transistors 11(a) and 11(b). The sense amplifier 5 determines whether the data is "0" or "1", and outputs it via a buffer circuit 6.
While the sense amplifier 5 is sensing data, an unstable state influences the buffer circuit 6 or data to be output. More specifically, the following drawback arises. In the memory cell selection process, the currently-selected bit and word lines are not changed to new ones instantaneously, but there occurs a difference in time between the selection of the current bit and word lines and that of the new ones. Just then, data of a memory cell other than a desired memory cell is read. If the read data is determined as data opposite to desired data by the sense amplifier, it is reversed. Thus, a large-sized transistor in the buffer circuit 6 repeats turning on and turning off until the data is determined by the sense amplifier, which is likely to be a noise source of a power line. The noise source adversely affects access time.
To eliminate the above drawback, an ATD (address transition detector) circuit 7 for detecting a transition of an address signal and generating a pulse is employed to latch data until its subsequent data is determined by the sense amplifier and then output as readout data. More specifically, the ATD circuit 7 receives an address signal from the address buffer and generates a pulse. The pulse is controlled by a pulse width control circuit 8 so as to have a width required for determining data by the sense amplifier 5. A latch circuit 9 latches data to be read out in accordance with the width of the pulse. When an address signal is changed to a new one, the latch circuit 9 still latches old data, which is obtained before the address signal is changed, by the functions of the ATD circuit 7 and pulse width control circuit 8. When new data is determined by the sense amplifier 5, the pulse supplied to the latch circuit 9, and the latch circuit 9 transfers the new data to the buffer circuit 6 in response to the new address signal. The new data is then output as new readout data.
In the foregoing circuit arrangement, since both the buffer circuit 6 and readout data are stable even while the sense amplifier 5 is sensing its subsequent data, noise can be eliminated, with the result that an access operation can be performed at high speed.
If, however, data of the sense amplifier 5 is reversed before its preceding data is latched in response to the pulse generated from the ATD circuit 7, data opposite to the preceding data is latched, which causes noise. The pulse transmitted to the latch circuit 9 has an unignorable delay due to gate delays of the ATD circuit 7 and pulse width control circuit 8 or wiring delays caused by wiring resistance and wiring capacity. Therefore, the column decoders 21 and 22 are operated at high speed, and the bit lines (column selection lines) are switched quickly. If, in this case, data of a selected memory cell is opposite to its preceding data to be latched, the opposite data is input to the latch circuit 9 through the sense amplifier 5 before the pulse is input thereto. Thus, the opposite data is latched.
There may be a case where, when a row selection signal is switched very quickly and a row selection line is changed accordingly, data of a memory cell acquired by this change is opposite to its preceding data, and the reversed data of the sense amplifier rises earlier than the pulse from the ATD does. In a nonvolatile memory, generally, the word lines are connected to the gates of a plurality of memory cells and, even though a word line selection signal is changed very quickly, it takes time to increase the gate potential of the memory cells over the threshold value of the "1+ data cells so that data can be read out. Actually, in most cases, access time is controlled by the rise of word lines. Therefore, it is bit lines (column selection lines) that are switched quickly.
As has been known conventionally, in a nonvolatile memory, "1+ data is read out very quickly in the column direction. The reason is as follows. A nonselected bit line of about 0 V corresponds to the "1+ data due to discharge from the drain junction of memory cells. When "1+ data is read out through the bit line of 0 V, the sense amplifier is to read out the "1+ data simply because a bit line is switched. All signals supplied to address pins are likely to be changed, depending upon where a selected cell is located, and all address buffers are operated to cause a large current to flow in all the chips. If the large current flows, the potential at the power line is lowered instantaneously. If the control circuit 8 is weaker to noise than the sense amplifier 5, the rise of a pulse signal deteriorates and the timing at which data is latched is delayed. If, furthermore, the latch circuit 9 is located far away from the ATD circuit 7 for generating a pulse, the wiring resistance and wiring capacity are increased to an unignorable extent, with the result that the timing at which data is latched is delayed more and more.
When the foregoing drawbacks occur, "1+ data, which is read out quickly in a "1+ data read mode, is latched.
In short, the conventional memory device has the following drawback. When an address signal is changed to a new one, if data of the sense amplifier is reversed in response to the new address signal before the preceding data, which is obtained before the address signal is changed, is latched in response to a pulse generated from the ATD circuit, the reversed data is latched, which causes noise.